S912XHZ512F1VAG Datasheet, PDF (336/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 7 Clocks and Reset Generator (S12CRGV6)
7.3.2 Register Descriptions
This section describes in address order all the CRG registers and their individual bits.
Register
Name
Bit 7
0x_00
R
0
SYNR
W
6
5
4
3
2
1
Bit 0
0
SYN5
SYN4
SYN3
SYN2
SYN1
SYN0
0x_01
R
0
REFDV _W
0
REFDV5 REFDV4 REFDV3 REFDV2 REFDV1 REFDV0
0x_02
R
0
0
0
0
0
0
0
0
CTFLG
W
0x_03
R
CRGFLG _W ^RTIF
PORF
LVRF
LOCKIF
LOCK
TRACK
SCMIF
SCM
0x_04
R
CRGINT _W ^RTIE
ILAF
0
0
LOCKIE
0
0
SCMIE
0x_05
R
0
CLKSEL
PLLSEL
W
PSTP
0
0
PLLWAI
RTIWAI COPWAI
0x_06
R
PLLCTL
W
CME
PLLON
AUTO
ACQ
FSTWKP
PRE
PCE
SCME
0x_07
RTICTL
R
RTDEC
W
RTR6
RTR5
RTR4
RTR3
RTR2
RTR1
RTR0
0x_08
R
0
0
COPCTL
WCOP
W
RSBCK
WRTMASK
0
CR2
CR1
CR0
0x_09
R
0
0
0
0
0
0
0
0
FORBYP _W
0x_0A
R
1
0
0
0
0
0
0
0
CTCTL
W
0x_0B
R
ARMCOP _W
0
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
= Unimplemented or Reserved
Figure 7-3. S12CRGV6 Register Summary
MC9S12XHZ512 Data Sheet, Rev. 1.06
336
Freescale Semiconductor