S912XHZ512F1VAG Datasheet, PDF (37/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 1 MC9S12XHZ Family Device Overview
1.2.3.3 TEST — Test Pin
This input only pin is reserved for test. This pin has a pulldown device.
NOTE
The TEST pin must be tied to V_SS in all applications.
1.2.3.4 XFC — PLL Loop Filter Pin
Please ask your Freescale representative for the interactive application note to compute PLL loop filter
elements. Any current leakage on this pin must be avoided.
MCU
V_DDPLL
C_S
R₀
V_DDPLL
C_P
XFC
Figure 1-6. PLL Loop Filter Connections
1.2.3.5 BKGD / MODC — Background Debug and Mode Pin
The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It
is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit
at the rising edge of RESET. The BKGD pin has a pullup device.
1.2.3.6 PAD[7:0] / AN[7:0] / KWAD[7:0] — Port AD I/O Pins [7:0]
PAD7–PAD0 are general-purpose input or output pins and analog inputs for the analog-to-digital
converter. They can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
1.2.3.7 PA[7:0] / ADDR[15:8] / IVD[15:8] — Port A I/O Pins
PA[7:0] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the external address bus. In MCU emulation modes of operation, these pins are used for external
address bus and internal visibility read data.
1.2.3.8 PB[7:1] / ADDR[7:1] / IVD[7:1] — Port B I/O Pins
PB[7:1] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the external address bus. In MCU emulation modes of operation, these pins are used for external
address bus and internal visibility read data.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
37