S912XHZ512F1VAG Datasheet, PDF (128/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
2.5 Resets
The reset values of all registers are given in the register description in Section 2.3, “Memory Map and
Register Definition”.
All ports start up as general-purpose inputs on reset.
2.5.1 Reset Initialization
All registers including the data registers get set/reset asynchronously. Table 2-67 summarizes the port
properties after reset initialization.
P
Table 2-67. Port Reset State Summary
Port
Reset States
Data
Direction
Pull Mode
A
Input
Pull Down
B
Input
Pull Down
C
Input
Hi-z
D
Input
Hi-z
E
Input
Pull Down¹
K
Input
Pull Down
AD
Input
Hi-z
L
Input
Pull Down
M
Input
Hi-z
P
Input
Hi-z
S
Input
Hi-z
T[7:4]
Input
Hi-z
T[3:0]
Input
Pull Down
U
Input
Hi-z
V
Input
Hi-z
W
Input
Hi-z
1 _{PE[1:0] pins have pull-ups instead of pull-downs.}
Reduced
Drive
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Slew Rate
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
N/A
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Wired-OR
Mode
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Disabled
Disabled
Disabled
Disabled
Disabled
N/A
N/A
N/A
Interrupt
N/A
N/A
N/A
N/A
N/A
N/A
Disabled
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MC9S12XHZ512 Data Sheet, Rev. 1.06
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Freescale Semiconductor