S912XHZ512F1VAG Datasheet, PDF (115/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

2.3.12.4 Port U Slew Rate Register (SRRU)
Chapter 2 Port Integration Module (S12XHZPIMV1)
Module Base + 0x003B
R
W
Reset
7
SRRU7
0
6
SRRU6
5
SRRU5
4
SRRU4
3
SRRU3
2
SRRU2
0
0
0
0
0
Figure 2-69. Port U Slew Rate Register (SRRU)
1
SRRU1
0
0
SRRU0
0
Read: Anytime. Write: Anytime.
This register enables the slew rate control and disables the digital input buffer for port pins PU[7:0].
Table 2-54. SRRU Field Descriptions
Field
Description
7:0
Slew Rate Port U
SRRU[7:0] 0 Disables slew rate control and enables digital input buffer.
1 Enables slew rate control and disables digital input buffer.
2.3.12.5 Port U Pull Device Enable Register (PERU)
Module Base + 0x003C
7
R
PERU7
W
6
PERU6
5
PERU5
4
PERU4
3
PERU3
2
PERU2
1
PERU1
0
PERU0
Reset
0
0
0
0
0
0
0
0
Figure 2-70. Port U Pull Device Enable Register (PERU)
Read: Anytime. Write: Anytime.
This register configures whether a pull-up or a pull-down device is activated on configured input pins. If
a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect.
Table 2-55. PERU Field Descriptions
Field
7:0
Pull Device Enable Port U
PERU[7:0] 0 Pull-up or pull-down device is disabled.
1 Pull-up or pull-down device is enabled.
Description
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
115