S912XHZ512F1VAG Datasheet, PDF (139/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 3 512 Kbyte Flash Module (S12XFTX512K4V3)
3.3.2.3 Flash Test Mode Register (FTSTMOD)
The FTSTMOD register is used to control Flash test features.
Module Base + 0x0002
7
6
5
4
3
2
1
0
R
0
W
MRDS
0
0
0
0
0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 3-6. Flash Test Mode Register (FTSTMOD —Normal Mode)
Module Base + 0x0002
7
6
5
4
3
2
1
0
R
0
W
MRDS
0
0
0
0
WRALL
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 3-7. Flash Test Mode Register (FTSTMOD — Special Mode)
MRDS bits are readable and writable while all remaining bits read 0 and are not writable in normal mode.
The WRALL bit is writable only in special mode to simplify mass erase and erase verify operations. When
writing to the FTSTMOD register in special mode, all unimplemented/reserved bits must be written to 0.
Table 3-6. FTSTMOD Field Descriptions
Field
Description
6:5
Margin Read Setting — The MRDS[1:0] bits are used to set the sense-amp margin level for reads of the Flash
MRDS[1:0] array as shown in Table 3-7.
4
WRALL
Write to all Register Banks — If the WRALL bit is set, all banked FDATA registers sharing the same register
address will be written simultaneously during a register write.
0 Write only to the FDATA register bank selected using BKSEL.
1 Write to all FDATA register banks.
Table 3-7. FTSTMOD Margin Read Settings
MRDS[1:0]
Margin Read Setting
00
Normal
01
Program Margin¹
10
Erase Margin²
11
Normal
1 Flash array reads will be sensitive to program margin.
2 Flash array reads will be sensitive to erase margin.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
139