S912XHZ512F1VAG Datasheet, PDF (50/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 1 MC9S12XHZ Family Device Overview
1.5.1.3 Special Single-Chip Mode
This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The
background debug module BDM is active in this mode. The CPU executes a monitor program located in
an on-chip ROM. BDM firmware is waiting for additional serial commands through the BKGD pin. There
is no external bus after reset in this mode.
1.5.1.4 Emulation of Expanded Mode
Developers use this mode for emulation systems in which the users target application is normal expanded
mode. Code is executed from external memory or from internal memory depending on the state of
ROMON and EROMON bit. In this mode the internal operation is visible on external bus interface.
1.5.1.5 Emulation of Single-Chip Mode
Developers use this mode for emulation systems in which the user’s target application is normal
single-chip mode. Code is executed from external memory or from internal memory depending on the state
of ROMON and EROMON bit. In this mode the internal operation is visible on external bus interface.
1.5.1.6 Special Test Mode
Freescale internal use only.
1.5.2 Low-Power Modes
The microcontroller features two main low-power modes. Consult the respective block description chapter
for information on the module behavior in system stop, system pseudo stop, and system wait mode. An
important source of information about the clock system is the Clock and Reset Generator (CRG) block
description chapter.
1.5.2.1 System Stop Modes
The system stop modes are entered if the CPU executes the STOP instruction and the XGATE doesn’t
execute a thread and the XGFACT bit in the XGMCTL register is cleared. Depending on the state of the
PSTP bit in the CLKSEL register the MCU goes into pseudo stop mode or full stop mode. Please refer to
CRG block description chapter. Asserting RESET, XIRQ, IRQ or any other interrupt ends the system stop
modes.
1.5.2.2 Pseudo Stop Mode
In this mode the clocks are stopped but the oscillator is still running and the real time interrupt (RTI) or
watchdog (COP) submodule can stay active. Other peripherals are turned off. This mode consumes more
current than the system stop mode, but the wake up time from this mode is significantly shorter.
1.5.2.3 Full Stop Mode
The oscillator is stopped in this mode. All clocks are switched off. All counters and dividers remain frozen.
MC9S12XHZ512 Data Sheet, Rev. 1.06
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Freescale Semiconductor