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S912XHZ512F1VAG Datasheet, PDF (686/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256 | |||
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Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
Table 19-12. TCTL3/TCTL4 Field Descriptions
Field
Description
EDG[7:0]B
7, 5, 3, 1
EDG[7:0]A
6, 4, 2, 0
Input Capture Edge Control â These eight pairs of control bits conï¬gure the input capture edge detector
circuits for each input capture channel. The four pairs of control bits in TCTL4 also conï¬gure the input capture
edge control for the four 8-bit pulse accumulators PAC0âPAC3.EDG0B and EDG0A in TCTL4 also determine the
active edge for the 16-bit pulse accumulator PACB. See Table 19-13.
Table 19-13. Edge Detector Circuit Conï¬guration
EDGxB
0
0
1
1
EDGxA
0
1
0
1
Conï¬guration
Capture disabled
Capture on rising edges only
Capture on falling edges only
Capture on any edge (rising or falling)
19.3.2.10 Timer Interrupt Enable Register (TIE)
Module Base + 0x000C
7
6
5
4
3
2
1
0
R
C7I
C6I
C5I
C4I
C3I
C2I
C1I
C0I
W
Reset
0
0
0
0
0
0
0
0
Figure 19-15. Timer Interrupt Enable Register (TIE)
Read or write: Anytime
All bits reset to zero.
The bits C7IâC0I correspond bit-for-bit with the ï¬ags in the TFLG1 status register.
Table 19-14. TIE Field Descriptions
Field
7:0
C[7:0]I
Description
Input Capture/Output Compare âxâ Interrupt Enable
0 The corresponding ï¬ag is disabled from causing a hardware interrupt.
1 The corresponding ï¬ag is enabled to cause an interrupt.
MC9S12XHZ512 Data Sheet, Rev. 1.06
686
Freescale Semiconductor
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