S912XHZ512F1VAG Datasheet, PDF (685/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
Table 19-11. The OC7 and OCx event priority
OC7M7=0
OC7Mx=1
TC7=TCx
TC7>TCx
OC7Mx=0
TC7=TCx
TC7>TCx
IOCx=OC7Dx IOCx=OC7Dx
IOC7=OM7/O +OMx/OLx
L7
IOC7=OM7/O
L7
IOCx=OMx/OLx
IOC7=OM7/OL7
OC7M7=1
OC7Mx=1
TC7=TCx
TC7>TCx
OC7Mx=0
TC7=TCx
TC7>TCx
IOCx=OC7Dx IOCx=OC7Dx
IOC7=OC7D7 +OMx/OLx
IOC7=OC7D7
IOCx=OMx/OLx
IOC7=OC7D7
Note: in Table 19-11,the IOS7 and IOSx should be set to 1
IOSx is the register TIOS bit x,
OC7Mx is the register OC7M bit x,
TCx is timer Input Capture/Output Compare register,
IOCx is channel x,
OMx/OLx is the register TCTL1/TCTL2,
OC7Dx is the register OC7D bit x.
IOCx = OC7Dx+ OMx/OLx, means that both OC7 event and OCx event will change channel x value.
19.3.2.9 Timer Control Register 3/Timer Control Register 4 (TCTL3/TCTL4)
Module Base + 0x000A
R
W
Reset
7
EDG7B
0
6
EDG7A
5
EDG6B
4
EDG6A
3
EDG5B
2
EDG5A
0
0
0
0
0
Figure 19-13. Timer Control Register 3 (TCTL3)
1
EDG4B
0
0
EDG4A
0
Module Base + 0x000B
R
W
Reset
7
EDG3B
0
6
EDG3A
5
EDG2B
4
EDG2A
3
EDG1B
2
EDG1A
0
0
0
0
0
Figure 19-14. Timer Control Register 4 (TCTL4)
Read or write: Anytime
All bits reset to zero.
1
EDG0B
0
0
EDG0A
0
MC9S12XHZ512 Data Sheet Rev. 1.06
Freescale Semiconductor
685