S912XHZ512F1VAG Datasheet, PDF (65/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3 Memory Map and Register Definition
This section provides a detailed description of all registers. Table 2-2 is a standard memory map of port
integration module.
Table 2-2. S12XHZPIM Memory Map
Address Offset
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000A - 0x000B
0x000C
0x000D
0x000E - 0x001B
0x001C
0x001D
0x001E
0x001F
0x0020 - 0x0031
0x0032
0x0033
0x0034 - 0x01FF
0x0200
0x0201
0x0202
0x0203
0x0204
0x0205
0x0206
0x0207
Use
Port A I/O Register (PTA)
Port B I/O Register (PTB)
Port A Data Direction Register (DDRA)
Port B Data Direction Register (DDRB)
Port C I/O Register (PTC)
Port D I/O Register (PTD)
Port C Data Direction Register (DDRC)
Port D Data Direction Register (DDRD)
Port E I/O Register (PTE)
Port E Data Direction Register (DDRE)
Non-PIM address range
Pull Up/Down Control Register (PUCR)
Reduced Drive Register (RDRIV)
Non-PIM address range
ECLK Control Register (ECLKCR)
Reserved
IRQ Control Register (IRQCR)
Slew Rate Control Register (SRCR)
Non-PIM address range
Port K I/O Register (PTK)
Port K Data Direction Register (DDRK)
Non-PIM address range
Port T I/O Register (PTT)
Port T Input Register (PTIT)
Port T Data Direction Register (DDRT)
Port T Reduced Drive Register (RDRT)
Port T Pull Device Enable Register (PERT)
Port T Polarity Select Register (PPST)
Port T Wired-OR Mode Register (WOMT)
Port T Slew Rate Register (SRRT)
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
—
R/W
—
R/W
R/W
—
R/W
R/W
—
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
65