S912XHZ512F1VAG Datasheet, PDF (102/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.10 Port S
Port S is associated with the chip select 3, the serial peripheral interface (SPI) and the serial
communication interface (SCI0). Each pin is assigned to these modules according to the following
priority: CS3 > SPI/SCI1/SCI0 > general-purpose I/O.
When the SPI is enabled, the PS[7:4] pins become SS, SCK, MOSI, and MISO respectively. Refer to the
SPI block description chapter for information on enabling and disabling the SPI.
When the SCI0 receiver and transmitter are enabled, the PS[1:0] pins become TXD0 and RXD0
respectively. When the SCI1 receiver and transmitter are enabled and MODRR2 is set, the PS[3:2] pins
become TXD1 and RXD1 respectively. Refer to the SCI block description chapter for information on
enabling and disabling the SCI receiver and transmitter.
During reset, port S pins are configured as high-impedance inputs.
2.3.10.1 Port S I/O Register (PTS)
Module Base + 0x0008
R
W
SPI/
SCI1/SCI0:
Chip
Select:
Reset
7
PTS7
SS
0
6
PTS6
5
PTS5
4
PTS4
3
PTS3
2
PTS2
SCK
MOSI
MISO
TXD1
RXD1
CS3
0
0
0
0
0
= Reserved or Unimplemented
Figure 2-50. Port S I/O Register (PTS)
1
PTS1
TXD0
0
0
PTS0
RXD0
0
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDRSx) is set to 1 (output), a read returns the value of the I/O register
bit. If the associated data direction bit (DDRSx) is set to 0 (input), a read returns the value of the pin.
The SPI function takes precedence over the general-purpose I/O function if the SPI is enabled.
If enabled, the SCI0(1) transmitter takes precedence over the general-purpose I/O function, and the
corresponding TXD0(1) pin is configured as an output. If enabled, the SCI0(1) receiver takes precedence
over the general-purpose I/O function, and the corresponding RXD0(1) pin is configured as an input.
MC9S12XHZ512 Data Sheet, Rev. 1.06
102
Freescale Semiconductor