S912XHZ512F1VAG Datasheet, PDF (126/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on the
Input Register when changing the Data Direction Register.
2.4.3 Data Direction Register
The Data Direction Register defines whether the pin is used as an input or an output.
. A Data Direction Register bit set to 0 configures the pin as an input. A Data Direction Register bit set to
1 configures the pin as an output. If a peripheral module controls the pin the contents of the data direction
register is ignored (Figure 2-84).
PTIx
0
1
PTx
0
1
PAD
DDRx
0
1
Digital ^{data out}
Module ^{output enable}
module enable
Figure 2-84. Illustration of I/O Pin Functionality
Figure 2-85 shows the state of digital inputs and outputs when an analog module drives the port. When the
analog module is enabled all associated digital output ports are disabled and all associated digital input
ports read “1”t.
Digital
Input
11
0
Module
Enable
Analog
Module
Analog
Output
Digital
Output
0
1
PAD
PIM Boundary
Figure 2-85. Digital Ports and Analog Module
MC9S12XHZ512 Data Sheet, Rev. 1.06
126
Freescale Semiconductor