S912XHZ512F1VAG Datasheet, PDF (88/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.7.2 Port L Input Register (PTIL)
Module Base + 0x0031
R
W
Reset
7
PTIL7
1
6
PTIL6
5
PTIL5
4
PTIL4
3
PTIL3
2
PTIL2
1
1
1
1
1
= Reserved or Unimplemented
Figure 2-28. Port L Input Register (PTIL)
1
PTIL1
1
0
PTIL0
1
Read: Anytime. Write: Never, writes to this register have no effect.
If the LCD frontplane driver of an associated I/O pin is enabled (and LCD module is enabled) or the
associated ATDDIEN0 bit is set to 0 (digital input buffer is disabled), a read returns a 1.
If the LCD frontplane driver of an associated I/O pin is disabled (or LCD module is disabled) and the
associated ATDDIEN0 bit is set to 1 (digital input buffer is enabled), a read returns the status of the
associated pin.
2.3.7.3 Port L Data Direction Register (DDRL)
Module Base + 0x0032
R
W
Reset
7
DDRL7
0
6
DDRL6
5
DDRL5
4
DDRL4
3
DDRL3
2
DDRL2
0
0
0
0
0
Figure 2-29. Port L Data Direction Register (DDRL)
1
DDRL1
0
0
DDRL0
0
Read: Anytime. Write: Anytime.
This register configures port pins PL[7:0] as either input or output.
If a LCD frontplane driver is enabled (and LCD module is enabled), it outputs an analog signal to the
corresponding pin and the associated Data Direction Register bit has no effect. If a LCD frontplane driver
is disabled (or LCD module is disabled), the corresponding Data Direction Register bit reverts to control
the I/O direction of the associated pin.
Table 2-21. DDRL Field Descriptions
Field
7:0
Data Direction Port L
DDRL[7:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
MC9S12XHZ512 Data Sheet, Rev. 1.06
88
Freescale Semiconductor