S912XHZ512F1VAG Datasheet, PDF (704/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
PTPS7
0
0
0
0
0
0
0
0
0
0
0
0
1
Table 19-34. Precision Timer Prescaler Selection Examples when PRNT = 1
PTPS6
0
0
0
0
0
0
0
0
0
0
0
1
1
PTPS5
0
0
0
0
0
0
0
0
0
0
1
1
1
PTPS4
0
0
0
0
0
0
0
0
0
1
1
1
1
PTPS3
0
0
0
0
0
0
0
0
1
1
1
1
1
PTPS2
0
0
0
0
1
1
1
1
1
1
1
1
1
PTPS1
0
0
1
1
0
0
1
1
1
1
1
1
1
PTPS0
0
1
0
1
0
1
0
1
1
1
1
1
1
Prescale
Factor
1
2
3
4
5
6
7
8
16
32
64
128
256
19.3.2.27 Precision Timer Modulus Counter Prescaler Select Register (PTMCPSR)
Module Base + 0x002F
R
W
Reset
7
PTMPS7
0
6
PTMPS6
0
5
PTMPS5
0
4
PTMPS4
0
3
PTMPS3
0
2
PTMPS2
0
1
PTMPS1
0
0
PTMPS0
0
Figure 19-50. Precision Timer Modulus Counter Prescaler Select Register (PTMCPSR)
Read: Anytime
Write: Anytime
All bits reset to zero.
Table 19-35. PTMCPSR Field Descriptions
Field
Description
7:0
Precision Timer Modulus Counter Prescaler Select Bits — These eight bits specify the division rate of the
PTMPS[7:0] modulus counter prescaler. These are effective only when the PRNT bit of TSCR1 is set to 1. Table 19-36 shows
some possible division rates.
The newly selected prescaler division rate will not be effective until a load of the load register into the modulus
counter count register occurs.
MC9S12XHZ512 Data Sheet, Rev. 1.06
704
Freescale Semiconductor