S912XHZ512F1VAG Datasheet, PDF (817/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 23 External Bus Interface (S12XEBIV3)
2 _{Refer to S12X_MMC section.}
3 _{If EWAITE = 1, the minimum number of external bus cycles is 3.}
4 _{Available only if configured appropriately by ROMON and EROMON (refer to S12X_MMC section).}
23.4.2 Internal Visibility
Internal visibility allows the observation of the internal CPU address and data bus as well as the
determination of the access source and the CPU pipe (queue) status through the external bus interface.
Internal visibility is always enabled in emulation single chip mode and emulation expanded mode. Internal
CPU accesses are made visible on the external bus interface except CPU execution of BDM firmware
instructions.
Internal reads are made visible on ADDRx/IVDx (address and read data multiplexed, see Table 23-10 to
Table 23-12), internal writes on ADDRx and DATAx (see Table 23-13 to Table 23-15). RW and LSTRB
show the type of access. External read data are also visible on IVDx.
During ‘no access’ cycles RW is held in read position while LSTRB is undetermined.
All accesses which make use of the external bus interface are considered external accesses.
23.4.2.1 Access Source Signals (ACC)
The access source can be determined from the external bus control signals ACC[2:0] as shown in
Table 23-8.
Table 23-8. Determining Access Source from Control Signals
ACC[2:0]
Access Description
000
Repetition of previous access cycle
001
CPU access
010
BDM external access
011
XGATE PRR access
100
No access¹
101
CPU access error
110, 111
Reserved
1 _{Denotes also CPU accesses to BDM firmware and BDM registers (IQSTATx}
are ‘XXXX’ and RW = 1 in these cases)
23.4.2.2 Instruction Queue Status Signals (IQSTAT)
The CPU instruction queue status (execution-start and data-movement information) is brought out as
IQSTAT[3:0] signals. For decoding of the IQSTAT values, refer to the S12X_CPU section.
23.4.2.3 Internal Visibility Data (IVD)
Depending on the access size and alignment, either a word of read data is made visible on the address lines
or only the related data byte will be presented in the ECLK low phase. For details refer to Table 23-9.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
817