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S912XHZ512F1VAG Datasheet, PDF (856/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256 | |||
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Chapter 25 Memory Mapping Control (S12XMMCV3)
Table 25-5. MMCCTL0 Field Descriptions
Field
3â0
CS[3:0]E
Description
Chip Select Enables â Each of these bits enables one of the external chip selects CS3, CS2, CS1, and CS0
outputs which are asserted during accesses to speciï¬c external addresses. The associated global address
ranges are shown in Table 25-6 and Table 25-21 and Figure 25-21.
Chip selects are only active if enabled in normal expanded mode, Emulation expanded mode and special test
mode. The function disabled in all other operating modes.
0 Chip select is disabled
1 Chip select is enabled
Table 25-6. Chip Select Signals
Global Address Range
Asserted Signal
0x00_0800â0x0F_FFFF
CS3
0x10_0000â0x1F_FFFF
CS2
0x20_0000â0x3F_FFFF
CS1
0x40_0000â0x7F_FFFF
CS01
1 When the internal NVM is enabled (see ROMON in Section 25.3.2.5, âMMC Control
Register (MMCCTL1)) the CS0 is not asserted in the space occupied by this on-chip
memory block.
MC9S12XHZ512 Data Sheet, Rev. 1.06
856
Freescale Semiconductor
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