S912XHZ512F1VAG Datasheet, PDF (241/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 5 XGATE (S12XGATEV2)
5.8.2.5 Bit Field Operations
This addressing mode is used to identify the position and size of a bit field for insertion or extraction. The
width and offset are coded in the lower byte of the source register 2, RS2. The content of the upper byte is
ignored. An offset of 0 denotes the right most position and a width of 0 denotes 1 bit. These instructions
are very useful to extract, insert, clear, set or toggle portions of a 16 bit word.
W4
O4
RS2
15
5
20
W4=3, O4=2
RS1
Bit Field Extract
Bit Field Insert
15
3
0
RD
BFEXT
Figure 5-23. Bit Field Addressing
R3,R4,R5 ; R5: W4 bits offset O4, will be extracted from R4 into R3
5.8.2.6 Special Instructions for DMA Usage
The XGATE offers a number of additional instructions for flag manipulation, program flow control and
debugging:
1. SIF: Set a channel interrupt flag
2. SSEM: Test and set a hardware semaphore
3. CSEM: Clear a hardware semaphore
4. BRK: Software breakpoint
5. NOP: No Operation
6. RTS: Terminate the current thread
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
241