S912XHZ512F1VAG Datasheet, PDF (415/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 10 Liquid Crystal Display (LCD32F4BV1) Block Description
10.3.2 Register Descriptions
This section consists of register descriptions. Each description includes a standard register diagram.
Details of register bit and field function follow the register diagrams, in bit order.
10.3.2.1 LCD Control Register 0 (LCDCR0)
Module Base + 0x0000
7
6
5
4
3
2
R
0
LCDEN
W
LCLK2
LCLK1
LCLK0
BIAS
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-2. LCD Control Register 0 (LCDCR0)
1
DUTY1
0
0
DUTY0
0
Read: anytime
Write: LCDEN anytime. To avoid segment flicker the clock prescaler bits, the bias select bit and the duty
select bits must not be changed when the LCD is enabled.
Table 10-3. LCDCR0 Field Descriptions
Field
Description
7
LCDEN
LCD32F4BV1 Driver System Enable — The LCDEN bit starts the LCD waveform generator.
0 All frontplane and backplane pins are disabled. In addition, the LCD32F4BV1 system is disabled
and all LCD waveform generation clocks are stopped.
1 LCD driver system is enabled. All FP[31:0] pins with FP[31:0]EN set, will output an LCD driver
waveform The BP[3:0] pins will output an LCD32F4BV1 driver waveform based on the settings of DUTY0
and DUTY1.
5:3
LCD Clock Prescaler — The LCD clock prescaler bits determine the OSCCLK divider value to produce the LCD
LCLK[2:0] clock frequency. For detailed description of the correlation between LCD clock prescaler bits and the divider
value please refer to Table 10-7.
2
BIAS
BIAS Voltage Level Select — This bit selects the bias voltage levels during various LCD operating modes, as
shown in Table 10-8.
1:0
LCD Duty Select — The DUTY1 and DUTY0 bits select the duty (multiplex mode) of the LCD32F4BV1 driver
DUTY[1:0] system, as shown in Table 10-8.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
415