S912XHZ512F1VAG Datasheet, PDF (504/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 13 Inter-Integrated Circuit (IICV3) Block Description
Clear
IBIF
Y
Master
N
Mode
?
TX
Tx/Rx
RX
?
Last Byte
Transmitted
Y
?
N
Clear IBAL
Y ^Arbitration
Lost
?
N
RXAK=0
?
N
Y
End Of
Y _{Addr Cycle}
(Master Rx)
?
N
Last
Byte To Be Read _Y
?
N
Y
2nd Last
Byte To Be Read
?
N
Write Next
Byte To IBDR
Set TXAK =1
Generate
Stop Signal
Switch To
Rx Mode
Dummy Read
From IBDR
Generate
Stop Signal
Read Data
From IBDR
And Store
N
IAAS=1
Y Y _IAAS=1
?
?
N
10-bit
address?
N
Y
Data Transfer
Y ^{7-bit address transfer}
(Read)
SRW=1
?
N ^(Write) Y
Set TX
Mode
TX/RX
?
TX
ACK From
Receiver
?
N
RX
10-bit address transfer
N _IBDR==
11110xx1?
Y
set RX
Mode
Write Data
To IBDR
Set RX
Mode
Tx Next
Byte
Read Data
From IBDR
And Store
set TX
Mode
Switch To
Rx Mode
Dummy Read
From IBDR
Write Data
To IBDR
Dummy Read
From IBDR
Dummy Read
From IBDR
RTI
Figure 13-16. Flow-Chart of Typical IIC Interrupt Routine
MC9S12XHZ512 Data Sheet, Rev. 1.06
504
Freescale Semiconductor