S912XHZ512F1VAG Datasheet, PDF (33/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 1 MC9S12XHZ Family Device Overview
1.2.2 Signal Properties Summary
Table 1-5 summarizes all pin functions.
Table 1-5. Signal Properties
Pin
Pin
Name
Name
Function 1 Function 2
Pin
Name
Function 3
Pin
Name
Function 4
Pin
Name
Function 5
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Internal Pull Up
Resistor
CTRL
Reset
State
Description
EXTAL
XTAL
RESET
TEST
XFC
BKGD
PAD[7:0]
PA[7:0]
PB[7:1]
PB0
PC[7:0]
PD[7:0]
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
—
—
—
—
—
MODC
AN[7:0]
FP[15:8]
FP[7:1]
FP0
—
—
FP22
TAGHI
TAGLO
ECLK
FP21
FP20
IRQ
XIRQ
—
—
—
—
—
—
KWAD[7:0]
ADDR[15:8]
ADDR[7:1]
ADDR0
DATA[15:8]
DATA[7:0]
ECLKX2
MODB
MODA
—
LSTRB
R/W
—
—
—
—
—
—
—
—
—
IVD[15:8]
IVD[7:1]
IVD0
—
—
—
—
—
—
—
—
—
UDS
V_DDPLL
V_DDPLL
V_DDX2
NA
V_DDPLL
V_DDX2
V_DDA
V_DDX1
V_DDX1
V_DDX1
—
—
XCLKS
—
V_DDX1
—
V_DDX1
—
V_DDX1
—
RE
—
LDS
WE
—
—
—
V_DDX2
—
V_DDX2
—
EROMCTL
V_DDX2
V_DDX1
—
V_DDX1
—
V_DDX2
—
V_DDX2
NA
NA Oscillator pins
NA
NA
PULL UP
External reset
NA
NA Test input - must be tied to
VSS in all applications
NA
NA PLL loop Filter
Always on
Up Background debug, mode
input
PERAD/ Disabled Port AD I/O, Analog inputs
PPSAD
(ATD), interrupts
PUCR
Down Port A I/O, address bus,
internal visibility data
PUCR
Down Port B I/O, address bus,
internal visibility data
PUCR
Down
Port B I/O, address bus,
internal visibility data,
upper data strobe
PUCR Disabled Port C I/O, data bus
PUCR Disabled Port D I/O, data bus
PUCR
Down
Port E I/O, LCD driver,
system clock output,
clock select
While RESET
pin is low: Down
Port E I/O, tag high, mode
input
While RESET
pin is low: Down
Port E I/O, tag low, mode input,
read enable
PUCR
Down Port E I/O, bus clock output
PUCR
Down Port E I/O, LCD driver, low byte
strobe, EROMON control
PUCR
Down Port E I/O, read/write, write
enable
PUCR
Up
Port E input, maskable
interrupt
PUCR
Up
Port E input, non-maskable
interrupt
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
33