S912XHZ512F1VAG Datasheet, PDF (97/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
The IIC function takes precedence over the general-purpose I/O function if the IIC bus is enabled and the
corresponding PWM channels remain disabled. The SDA and SCL pins are bidirectional with outputs
configured as open-drain.
If enabled, the SCI1 transmitter takes precedence over the general-purpose I/O function, and the
corresponding TXD1 pin is configured as an output. If enabled, the SCI1 receiver takes precedence over
the general-purpose I/O function, and the corresponding RXD1 pin is configured as an input.
2.3.9.2 Port P Input Register (PTIP)
Module Base + 0x0019
R
W
Reset
7
PTIP7
u
6
PTIP6
5
PTIP5
4
PTIP4
3
PTIP3
2
PTIP2
u
u
u
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 2-43. Port P I/O Register (PTP)
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
1
PTIP1
u
0
PTIP0
u
2.3.9.3 Port P Data Direction Register (DDRP)
Module Base + 0x001A
R
W
Reset
7
DDRP7
0
6
DDRP6
5
DDRP5
4
DDRP4
3
DDRP3
2
DDRP2
0
0
0
0
0
Figure 2-44. Port P Data Direction Register (DDRP)
1
DDRP1
0
0
DDRP0
0
Read: Anytime. Write: Anytime.
This register configures port pins PP[7:0] as either input or output.
If a PWM channel is enabled, the corresponding pin is forced to be an output and the associated Data
Direction Register bit has no effect. Channel 5 can also force the corresponding pin to be an input if the
shutdown feature is enabled.
When an IIC bus is enabled, the corresponding pins become the SCL and SDA bidirectional pins
respectively as long as the corresponding PWM channels are disabled. The associated Data Direction
Register bits have no effect.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
97