S912XHZ512F1VAG Datasheet, PDF (103/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

2.3.10.2 Port S Input Register (PTIS)
Chapter 2 Port Integration Module (S12XHZPIMV1)
Module Base + 0x0009
R
W
Reset
7
PTIS7
u
6
PTIS6
5
PTIS5
4
PTIS4
3
PTIS3
2
PTIS2
u
u
u
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 2-51. Port S Input Register (PTIS)
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
1
PTIS1
u
0
PTIS0
u
2.3.10.3 Port S Data Direction Register (DDRS)
Module Base + 0x000A
R
W
Reset
7
DDRS7
0
6
DDRS6
5
DDRS5
4
DDRS4
3
DDRS3
2
DDRS2
0
0
0
0
0
Figure 2-52. Port S Data Direction Register (DDRS)
1
DDRS1
0
0
DDRS0
0
Read: Anytime. Write: Anytime.
This register configures port pins PS[7:0] as either input or output.
When the SPI is enabled, the PS[7:4] pins become the SPI bidirectional pins. The associated Data
Direction Register bits have no effect.
When the SCI1 transmitter is enabled, the PS[3] pin becomes the TXD1 output pin and the associated Data
Direction Register bit has no effect. When the SCI1 receiver is enabled, the PS[2] pin becomes the RXD1
input pin and the associated Data Direction Register bit has no effect.
When the SCI0 transmitter is enabled, the PS[1] pin becomes the TXD0 output pin and the associated Data
Direction Register bit has no effect. When the SCI0 receiver is enabled, the PS[0] pin becomes the RXD0
input pin and the associated Data Direction Register bit has no effect.
If the SPI, SCI1 and SCI0 functions are disabled, the corresponding Data Direction Register bit reverts to
control the I/O direction of the associated pin.
Table 2-38. DDRS Field Descriptions
Field
7:0
Data Direction Port S
DDRS[7:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
103