S912XHZ512F1VAG Datasheet, PDF (729/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 20 Voltage Regulator (S12VREG3V3V5)
20.2.4 VDDPLL, VSSPLL — Regulator Output2 (PLL) Pins
Signals V_DDPLL/V_SSPLL are the secondary outputs of VREG_3V3 that provide the power supply for the
PLL and oscillator. These signals are connected to device pins to allow external decoupling capacitors
(100 nF...220 nF, X7R ceramic).
In shutdown mode, an external supply driving V_DDPLL/V_SSPLL can replace the voltage regulator.
20.2.5 V_{REGEN —} Optional Regulator Enable Pin
This optional signal is used to shutdown VREG_3V3. In that case, V_DD/V_SS and V_DDPLL/V_SSPLL must be
provided externally. Shutdown mode is entered with VREGEN being low. If VREGEN is high, the
VREG_3V3 is either in full peformance mode or in reduced power mode.
For the connectivity of VREGEN, see device specification.
NOTE
Switching from FPM or RPM to shutdown of VREG_3V3 and vice versa
is not supported while MCU is powered.
20.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in VREG_3V3.
If enabled in the system, the VREG_3V3 will abort all read and write accesses to reserved registers within
it’s memory slice.
20.3.1 Module Memory Map
Table 20-2 provides an overview of all used registers.
Table 20-2. Memory Map
Address
Offset
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
Use
HT Control Register (VREGHTCL)
Control Register (VREGCTRL)
Autonomous Periodical Interrupt Control Register (VREGAPICL)
Autonomous Periodical Interrupt Trimming Register (VREGAPITR)
Autonomous Periodical Interrupt Period High (VREGAPIRH)
Autonomous Periodical Interrupt Period Low (VREGAPIRL)
Reserved 06
Reserved 07
Access
—
R/W
R/W
R/W
R/W
R/W
—
—
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
729