S912XHZ512F1VAG Datasheet, PDF (67/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
Table 2-2. S12XHZPIM Memory Map (continued)
Address Offset
0x0240
0x0241
0x0242
0x0243
0x0244
0x0245
0x0246 - 0x0247
0x0248
0x0249
0x024A
0x024B
0x024C
0x024D
0x024E - 0x0250
0x0251
0x0252
0x0253
0x0254
0x0255
0x0256
0x0257
0x0258
0x0259
0x025A
0x025B
0x025C
0x025D
0x025E
0x025F
0x0260 - 0x027F
Use
Port V I/O Register (PTV)
Port V Input Register (PTIV)
Port V Data Direction Register (DDRV)
Port V Slew Rate Register (SRRV)
Port V Pull Device Enable Register (PERV)
Port V Polarity Select Register (PPSV)
Reserved
Port W I/O Register (PTW)
Port W Input Register (PTIW)
Port W Data Direction Register (DDRW)
Port W Slew Rate Register (SRRW)
Port W Pull Device Enable Register (PERW)
Port W Polarity Select Register (PPSW)
Reserved
Port AD I/O Register (PTAD)
Reserved
Port AD Input Register (PTIAD)
Reserved
Port AD Data Direction Register (DDRAD)
Reserved
Port AD Reduced Drive Register (RDRAD)
Reserved
Port AD Pull Device Enable Register (PERAD)
Reserved
Port AD Polarity Select Register (PPSAD)
Reserved
Port AD Interrupt Enable Register (PIEAD)
Reserved
Port AD Interrupt Flag Register (PIFAD)
Reserved
Access
R/W
R
R/W
R/W
R/W
R/W
—
R/W
R
R/W
R/W
R/W
R/W
—
R/W
—
R
—
R/W
—
R/W
—
R/W
—
R/W
—
R/W
—
R/W
—
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
67