S912XHZ512F1VAG Datasheet, PDF (395/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 9 Analog-to-Digital Converter (ATD10B16CV4) Block Description
9.3.2.7 ATD Status Register 0 (ATDSTAT0)
This read-only register contains the Sequence Complete Flag, overrun flags for external trigger and FIFO
mode, and the conversion counter.
Module Base + 0x0006
7
R
SCF
W
6
5
4
3
2
1
0
0
CC3
CC2
CC1
CC0
ETORF
FIFOR
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-9. ATD Status Register 0 (ATDSTAT0)
Read: Anytime
Write: Anytime (No effect on CC[3:0])
Table 9-18. ATDSTAT0 Field Descriptions
Field
7
SCF
5
ETORF
Description
Sequence Complete Flag — This flag is set upon completion of a conversion sequence. If conversion
sequences are continuously performed (SCAN = 1), the flag is set after each one is completed. This flag is
cleared when one of the following occurs:
• Write “1” to SCF
• Write to ATDCTL5 (a new conversion sequence is started)
• If AFFC = 1 and read of a result register
0 Conversion sequence not completed
1 Conversion sequence has completed
External Trigger Overrun Flag —While in edge trigger mode (ETRIGLE = 0), if additional active edges are
detected while a conversion sequence is in process the overrun flag is set. This flag is cleared when one of the
following occurs:
• Write “1” to ETORF
• Write to ATDCTL0,1,2,3,4 (a conversion sequence is aborted)
• Write to ATDCTL5 (a new conversion sequence is started)
0 No External trigger over run error has occurred
1 External trigger over run error has occurred
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
395