S912XHZ512F1VAG Datasheet, PDF (80/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.5.4 IRQ Control Register (IRQCR)
Module Base + 0x0055
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
IRQE
IRQEN
W
Reset
0
1
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 2-17. Port E Data Direction Register (DDRE)
Read: See individual bit descriptions below.
Write: See individual bit descriptions below.
Table 2-13. IRQCR Field Descriptions
Field
7
IRQE
6
IRQEN
Description
IRQ Select Edge Sensitive Only
Special modes: Read or write anytime.
Normal and emulation modes: Read anytime, write once.
0 IRQ configured for low level recognition.
1 IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime
IRQE = 1. The edge detector is cleared only upon the servicing of the IRQ interrupt or a reset .
External IRQ Enable
Read or write anytime.
0 External IRQ pin is disconnected from interrupt logic.
1 External IRQ pin is connected to interrupt logic.
MC9S12XHZ512 Data Sheet, Rev. 1.06
80
Freescale Semiconductor