S912XHZ512F1VAG Datasheet, PDF (75/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.4 Port K
Port K pins can be used for either general-purpose I/O, or the liquid crystal display (LCD) driver, or the
external address bus outputs ADDR22-ADDR16 muxed with master access output ACC2-ACC0 and
instruction pipe signals IQSTAT3-IQSTAT0, or inputs EWAIT and ROMCTL. Refer to the LCD block
description chapter for information on enabling and disabling the LCD and its frontplane drivers. Refer to
the S12X_EBI block description chapter for information on external bus.
2.3.4.1 Port K I/O Register (PTK)
Module Base + 0x0051
7
R
PTK7
W
XEBI: ROMCTL¹
or
EWAIT
6
PTK6
ADDR22
or
ACC2
5
PTK5
ADDR21
or
ACC1
4
PTK4
ADDR20
or
ACC0
3
PTK3
ADDR19
or
IQSTAT3
2
PTK2
ADDR18
or
IQSTAT2
LCD: FP23
BP3
BP2
Reset
0
0
0
0
0
0
Figure 2-12. Port K I/O Register (PTK)
1 _{Function active when RESET asserted.}
1
PTK1
ADDR17
or
IQSTAT1
BP1
0
0
PTK0
ADDR16
or
IQSTAT0
BP0
0
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDRKx) is set to 1 (output), a read returns the value of the I/O register
bit.
If the associated data direction bit (DDRKx) is set to 0 (input) and the LCD frontplane driver is enabled
(and LCD module is enabled), the associated I/O register bit (PTKx) reads “1”.
If the associated data direction bit (DDRKx) is set to 0 (input) and the LCD frontplane driver is disabled
(or LCD module is disabled), a read returns the value of the pin.
2.3.4.2 Port K Data Direction Register (DDRK)
Module Base + 0x0055
R
W
Reset
7
DDRK7
0
6
DDRK6
5
DDRK5
4
DDRK4
3
DDRK3
2
DDRK2
0
0
0
0
0
Figure 2-13. Port K Data Direction Register (DDRK)
Read: Anytime. Write: Anytime.
1
DDRK1
0
0
DDRK0
0
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
75