S912XHZ512F1VAG Datasheet, PDF (700/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.22 Delay Counter Control Register (DLYCT)
Module Base + 0x0029
R
W
Reset
7
DLY7
0
Read: Anytime
Write: Anytime
All bits reset to zero.
6
DLY6
5
DLY5
4
DLY4
3
DLY3
2
DLY2
0
0
0
0
0
Figure 19-45. Delay Counter Control Register (DLYCT)
1
DLY1
0
0
DLY0
0
Table 19-27. DLYCT Field Descriptions
Field
Description
7:0
DLY[7:0]
Delay Counter Select — When the PRNT bit of TSCR1 register is set to 0, only bits DLY0, DLY1 are used to
calculate the delay.Table 19-28 shows the delay settings in this case.
When the PRNT bit of TSCR1 register is set to 1, all bits are used to set a more precise delay. Table 19-29 shows
the delay settings in this case. After detection of a valid edge on an input capture pin, the delay counter counts
the pre-selected number of [(dly_cnt + 1)*4]bus clock cycles, then it will generate a pulse on its output if the level
of input signal, after the preset delay, is the opposite of the level before the transition.This will avoid reaction to
narrow input pulses.
Delay between two active edges of the input signal period should be longer than the selected counter delay.
Note: It is recommended to not write to this register while the timer is enabled, that is when TEN is set in register
TSCR1.
Table 19-28. Delay Counter Select when PRNT = 0
DLY1
0
0
1
1
DLY0
0
1
0
1
Delay
Disabled
256 bus clock cycles
512 bus clock cycles
1024 bus clock cycles
Table 19-29. Delay Counter Select Examples when PRNT = 1
DLY7
0
0
0
0
0
0
0
DLY6
0
0
0
0
0
0
0
DLY5
0
0
0
0
0
0
0
DLY4
0
0
0
0
0
0
0
DLY3
0
0
0
0
0
0
0
DLY2
0
0
0
0
1
1
1
DLY1
0
0
1
1
0
0
1
DLY0
0
1
0
1
0
1
0
Delay
Disabled (bypassed)
8 bus clock cycles
12 bus clock cycles
16 bus clock cycles
20 bus clock cycles
24 bus clock cycles
28 bus clock cycles
MC9S12XHZ512 Data Sheet, Rev. 1.06
700
Freescale Semiconductor