S912XHZ512F1VAG Datasheet, PDF (540/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)
14.3.3.3 Data Length Register (DLR)
This register keeps the data length field of the CAN frame.
Module Base + 0x00XC
7
6
5
4
3
2
1
R
DLC3
DLC2
DLC1
W
Reset:
x
x
x
x
x
x
x
= Unused; always read “x”
Figure 14-35. Data Length Register (DLR) — Extended Identifier Mapping
0
DLC0
x
Table 14-34. DLR Register Field Descriptions
Field
Description
3-0
DLC[3:0]
Data Length Code Bits — The data length code contains the number of bytes (data byte count) of the respective
message. During the transmission of a remote frame, the data length code is transmitted as programmed while
the number of transmitted data bytes is always 0. The data byte count ranges from 0 to 8 for a data frame.
Table 14-35 shows the effect of setting the DLC bits.
DLC3
0
0
0
0
0
0
0
0
1
Table 14-35. Data Length Codes
Data Length Code
DLC2
0
0
0
0
1
1
1
1
0
DLC1
0
0
1
1
0
0
1
1
0
DLC0
0
1
0
1
0
1
0
1
0
Data Byte
Count
0
1
2
3
4
5
6
7
8
14.3.3.4 Transmit Buffer Priority Register (TBPR)
This register defines the local priority of the associated message buffer. The local priority is used for the
internal prioritization process of the MSCAN and is defined to be highest for the smallest binary number.
The MSCAN implements the following internal prioritization mechanisms:
• All transmission buffers with a cleared TXEx flag participate in the prioritization immediately
before the SOF (start of frame) is sent.
MC9S12XHZ512 Data Sheet, Rev. 1.06
540
Freescale Semiconductor