S912XHZ512F1VAG Datasheet, PDF (113/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.12 Port U
Port U is associated with the stepper stall detect (SSD1 and SSD0) and motor controller (MC1 and MC0)
modules. Each pin is assigned to these modules according to the following priority: SSD1/SSD0 >
MC1/MC0 > general-purpose I/O.
If SSD1 module is enabled, the PU[7:4] pins are controlled by the SSD1 module. If SSD1 module is
disabled, the PU[7:4] pins are controlled by the motor control PWM channels 3 and 2 (MC1).
If SSD0 module is enabled, the PU[3:0] pins are controlled by the SSD0 module. If SSD0 module is
disabled, the PU[3:0] pins are controlled by the motor control PWM channels 1 and 0 (MC0).
Refer to the SSD and MC block description chapters for information on enabling and disabling the SSD
module and the motor control PWM channels respectively.
During reset, port U pins are configured as high-impedance inputs.
2.3.12.1 Port U I/O Register (PTU)
Module Base + 0x0038
7
R
PTU7
W
6
PTU6
5
PTU5
4
PTU4
3
PTU3
2
PTU2
1
PTU1
0
PTU0
MC: M1C1P
M1C1M
M1COP
M1COM
M0C1P
M0C1M
M0C0P
M0C0M
SSD1/
SSD0:
M1SINP
M1SINM M1COSP M1COSM M0SINP
M0SINM M1COSP M0COSM
Reset
0
0
0
0
0
0
0
0
Figure 2-66. Port U I/O Register (PTU)
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDRUx) is set to 1 (output), a read returns the value of the I/O register
bit.
If the associated data direction bit (DDRUx) is set to 0 (input) and the slew rate is enabled, the associated
I/O register bit (PTUx) reads “1”.
If the associated data direction bit (DDRUx) is set to 0 (input) and the slew rate is disabled, a read returns
the value of the pin.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
113