S912XHZ512F1VAG Datasheet, PDF (495/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

MSB
LSB
CL
1 2 34 5 6 78 9
Chapter 13 Inter-Integrated Circuit (IICV3) Block Description
MSB
LSB
1 2 34 5 6 78 9
DA
ADR7 ADR6 ADR5 ADR4ADR3 ADR2 ADR1R/W
XXX
D7 D6 D5 D4 D3 D2 D1 D0
Start
Signal
Calling Address
Read/ Ack
Write ^Bit
MSB
LSB
CL
1 2 34 5 67 89
Data Byte
No
Ack
Bit
MSB
LSB
1 234 5 678 9
DA
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1R/W
XX
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1R/W
Start
Signal
Calling Address
Read/ Ack
Write ^Bit
Repeated
Start
Signal
New Calling Address
Read/ No
Write
Ack
Bit
Figure 13-10. IIC-Bus Transmission Signals
13.4.1.1 START Signal
When the bus is free, i.e. no master device is engaging the bus (both SCL and SDA lines are at logical
high), a master may initiate communication by sending a START signal.As shown in Figure 13-10, a
START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the
beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves
out of their idle states.
SDA
SCL
START Condition
STOP Condition
Figure 13-11. Start and Stop Conditions
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
495