S912XHZ512F1VAG Datasheet, PDF (810/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 23 External Bus Interface (S12XEBIV3)
23.1.4 Block Diagram
Figure 23-1 is a block diagram of the XEBI with all related I/O signals.
ADDR[22:0]
DATA[15:0]
IVD[15:0]
EWAIT
XEBI
LSTRB
RW
UDS
LDS
RE
WE
Figure 23-1. XEBI Block Diagram
ACC[2:0]
IQSTAT[3:0]
23.2 External Signal Description
The user is advised to refer to the SoC section for port configuration and location of external bus signals.
NOTE
The following external bus related signals are described in other sections:
CS2, CS1, CS0 (chip selects) — S12X_MMC section
ECLK, ECLKX2 (free-running clocks) — PIM section
TAGHI, TAGLO (tag inputs) — PIM section, S12X_DBG section
Table 23-1 outlines the pin names and gives a brief description of their function. Refer to the SoC section
and PIM section for reset states of these pins and associated pull-ups or pull-downs.
MC9S12XHZ512 Data Sheet, Rev. 1.06
810
Freescale Semiconductor