S912XHZ512F1VAG Datasheet, PDF (101/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

2.3.9.8 Port P Slew Rate Register (SRRP)
Chapter 2 Port Integration Module (S12XHZPIMV1)
Module Base + 0x003B
R
W
Reset
7
SRRP7
0
6
SRRP6
5
SRRP5
4
SRRP4
3
SRRP3
2
SRRP2
0
0
0
0
0
Figure 2-49. Port P Slew Rate Register (SRRP)
1
SRRP1
0
0
SRRP0
0
Read: Anytime. Write: Anytime.
This register enables the slew rate control and disables the digital input buffer for port pins PP[7:0].
Table 2-37. SRRP Field Descriptions
Field
Description
7:0
Slew Rate Port P
SRRP[7:0] 0 Disables slew rate control and enables digital input buffer.
1 Enables slew rate control and disables digital input buffer.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
101