S912XHZ512F1VAG Datasheet, PDF (452/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 11 Motor Controller (MC10B12CV2) Block Description
value, DUTY, contained in D[10:1] in MCDCx. When a match (output compare between motor controller
timer counter and DUTY) occurs, the PWM output will toggle to a logic high level and will remain at a
logic high level until the motor controller timer counter overflows (reaches the value defined by P[10:1] – 1
in MCPER). After the motor controller timer counter resets to 0x000, the PWM output will return to a logic
low level. This completes the first half of the PWM period. During the second half of the PWM period, the
PWM output will remain at a logic low level until either the motor controller timer counter matches the
10-bit PWM duty cycle value, DUTY, contained in D[10:1] in MCDCx if D0 = 0, or the motor controller
timer counter matches the 10-bit PWM duty cycle value + 1 (the value of D[10:1] in MCDCx is increment
by 1 and is compared with the motor controller timer counter value) if D0 = 1 in the corresponding duty
cycle register. When a match occurs, the PWM output will toggle to a logic high level and will remain at
a logic high level until the motor controller timer counter overflows (reaches the value defined by P[10:1]
– 1 in MCPER). After the motor controller timer counter resets to 0x000, the PWM output will return to
a logic low level.
This process will repeat every number of counts of the motor controller timer counter defined by the period
register contents (P[10:0]). If the output is neither set to 0% nor to 100% there will be four edges on the
PWM output per PWM period in this case. Therefore, the PWM output compare function will alternate
between DUTY and DUTY + 1 every half PWM period if D0 in the corresponding duty cycle register is
set to 1. The relationship between the motor controller timer counter clock (f_TC), motor controller timer
counter value, and left aligned PWM output if DITH = 1 is shown in Figure 11-18 and Figure 11-19.
Figure 11-20 and Figure 11-21 show right aligned and center aligned PWM operation respectively, with
dither feature enabled and D0 = 1. Please note: In the following examples, the MCPER value is defined by
the bits P[10:0], which is, if DITH = 1, always an even number.
NOTE
The DITH bit must be changed only if the motor controller is disabled (all
channels disabled or period register cleared) to avoid erroneous waveforms.
Motor Controller
Timer Counter
Clock
Motor Controller
Timer Counter
0
15
16
99 0
15
16
99 0
PWM Output
100 Counts
1 Period
100 Counts
Figure 11-18. PWM Output: DITH = 1, MCAM[1:0] = 01, MCDC = 31, MCPER = 200, RECIRC = 0
MC9S12XHZ512 Data Sheet, Rev. 1.06
452
Freescale Semiconductor