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S912XHZ512F1VAG Datasheet, PDF (493/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256 | |||
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Chapter 13 Inter-Integrated Circuit (IICV3) Block Description
Table 13-9. IBSR Field Descriptions (continued)
Field
Description
3
Reserved â Bit 3 of IBSR is reserved for future use. A read operation on this bit will return 0.
RESERVED
2
SRW
Slave Read/Write â When IAAS is set this bit indicates the value of the R/W command bit of the calling address
sent from the master
This bit is only valid when the I-bus is in slave mode, a complete address transfer has occurred with an address
match and no other transfers have been initiated.
Checking this bit, the CPU can select slave transmit/receive mode according to the command of the master.
0 Slave receive, master writing to slave
1 Slave transmit, master reading from slave
1
I-Bus Interrupt â The IBIF bit is set when one of the following conditions occurs:
IBIF
â Arbitration lost (IBAL bit set)
â Data transfer complete (TCF bit set)
â Addressed as slave (IAAS bit set)
It will cause a processor interrupt request if the IBIE bit is set. This bit must be cleared by software, writing a one
to it. A write of 0 has no effect on this bit.
0
RXAK
Received Acknowledge â The value of SDA during the acknowledge bit of a bus cycle. If the received
acknowledge bit (RXAK) is low, it indicates an acknowledge signal has been received after the completion of 8
bits data transmission on the bus. If RXAK is high, it means no acknowledge signal is detected at the 9th clock.
0 Acknowledge received
1 No acknowledge received
13.3.1.5 IIC Data I/O Register (IBDR)
Module Base + 0x0004
7
6
5
4
3
2
1
0
R
D7
D6
D5
D4
D3
D2
D1
D0
W
Reset
0
0
0
0
0
0
0
0
Figure 13-8. IIC Bus Data I/O Register (IBDR)
In master transmit mode, when data is written to the IBDR a data transfer is initiated. The most signiï¬cant
bit is sent ï¬rst. In master receive mode, reading this register initiates next byte data receiving. In slave
mode, the same functions are available after an address match has occurred.Note that the Tx/Rx bit in the
IBCR must correctly reï¬ect the desired direction of transfer in master and slave modes for the transmission
to begin. For instance, if the IIC is conï¬gured for master transmit but a master receive is desired, then
reading the IBDR will not initiate the receive.
Reading the IBDR will return the last byte received while the IIC is conï¬gured in either master receive or
slave receive modes. The IBDR does not reï¬ect every byte that is transmitted on the IIC bus, nor can
software verify that a byte has been written to the IBDR correctly by reading it back.
In master transmit mode, the ï¬rst byte of data written to IBDR following assertion of MS/SL is used for
the address transfer and should com.prise of the calling address (in position D7:D1) concatenated with the
required R/W bit (in position D0).
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
493
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