S912XHZ512F1VAG Datasheet, PDF (440/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 11 Motor Controller (MC10B12CV2) Block Description
CD[1:0]
00
01
10
11
Table 11-9. Channel Delay
n [# of PWM Clocks]
0
1
2
3
NOTE
The PWM motor controller will release the pins after the next PWM timer
counter overflow without accommodating any channel delay if a single
channel has been disabled or if the period register has been cleared or all
channels have been disabled. Program one or more inactive PWM frames
(duty cycle = 0) before writing a configuration that disables a single channel
or the entire PWM motor controller.
11.3.2.5 Motor Controller Duty Cycle Registers
Each duty cycle register sets the sign and duty functionality for the respective PWM channel.
The contents of the duty cycle registers define DUTY, the number of motor controller timer counter clocks
the corresponding output is driven low (RECIRC = 0) or is driven high (RECIRC = 1). Setting all bits to 0
will give a static high output in case of RECIRC = 0; otherwise, a static low output. Values greater than or
equal to the contents of the period register will generate a static low output in case of RECIRC = 0, or a
static high output if RECIRC = 1. The layout of the duty cycle registers differ dependent upon the state of
the FAST bit in the control register 0.
Offset Module Base + 0x0020 . . . 0x0037
Access: User read/write
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R
SSSS
S
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 11-8. Motor Controller Duty Cycle Register x (MCDCx) with FAST = 0
MC9S12XHZ512 Data Sheet, Rev. 1.06
440
Freescale Semiconductor