S912XHZ512F1VAG Datasheet, PDF (774/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 22 S12X Debug (S12XDBGV3) Module
TRANGE
00
01
10
11
Table 22-12. TRANGE Trace Range Encoding
Tracing Range
Trace from all addresses (No filter)
Trace only in address range from $00000 to Comparator D
Trace only in address range from Comparator C to $7FFFFF
Trace only in range from Comparator C to Comparator D
Table 22-13. TRCMOD Trace Mode Bit Encoding
TRCMOD
00
01
10
11
Description
Normal
Loop1
Detail
Pure PC
Table 22-14. TALIGN Trace Alignment Encoding
TALIGN
00
01
10
11
Description
Trigger at end of stored data
Trigger before storing data
Trace buffer entries before and after trigger
Reserved
22.3.2.4 Debug Control Register2 (DBGC2)
Address: 0x0023
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
2
CDCM
0
0
Figure 22-6. Debug Control Register2 (DBGC2)
Read: Anytime
Write: Anytime the module is disarmed.
This register configures the comparators for range matching.
1
0
ABCM
0
0
Table 22-15. DBGC2 Field Descriptions
Field
Description
3–2
C and D Comparator Match Control — These bits determine the C and D comparator match mapping as
CDCM[1:0] described in Table 22-16.
1–0
A and B Comparator Match Control — These bits determine the A and B comparator match mapping as
ABCM[1:0] described in Table 22-17.
MC9S12XHZ512 Data Sheet, Rev. 1.06
774
Freescale Semiconductor