S912XHZ512F1VAG Datasheet, PDF (952/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Appendix E Detailed Register Map
0x00C0–0x00C7 Inter IC Bus (IIC0) Map
Address
0x00C0
0x00C1
0x00C2
0x00C3
0x00C4
0x00C5
0x00C6
0x00C7
Name
IB0AD
IB0FD
IB0CR
IB0SR
IB0DR
IB0CR2
Reserved
Reserved
Bit 7
R
ADR7
W
R
IBC7
W
R
IBEN
W
R TCF
W
R
D7
W
R
GCEN
W
R
0
W
R
0
W
Bit 6
ADR6
IBC6
IBIE
IAAS
D6
ADTYPE
0
0
Bit 5
ADR5
IBC5
MS/SL
IBB
D5
0
0
0
Bit 4
ADR4
IBC4
TX/RX
IBAL
D4
0
0
0
Bit 3
ADR3
IBC3
TXAK
0
D3
0
0
0
Bit 2
ADR2
IBC2
0
RSTA
SRW
D2
ADR10
0
0
Bit 1
ADR1
IBC1
0
IBIF
D1
ADR9
0
0
Bit 0
0
IBC0
IBSWAI
RXAK
D0
ADR8
0
0
0x00C8–0x00CF Asynchronous Serial Interface (SCI0) Map
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
0x00C8
0x00C9
0x00CA
0x00C8
0x00C9
0x00CA
0x00CB
0x00CC
0x00CD
0x00CE
0x00CF
SCI0BDH¹
SCI0BDL¹
SCI0CR1¹
SCI0ASR1²
SCI0ACR1²
SCI0ACR2²
SCI0CR2
SCI0SR1
SCI0SR2
SCI0DRH
SCI0DRL
R
IREN
W
R
SBR7
W
R
LOOPS
W
R
RXEDGIF
W
R
RXEDGIE
W
R
0
W
R
TIE
W
R TDRE
W
R
AMAP
W
R R8
W
R R7
W T7
TNP1
SBR6
SCISWAI
0
0
0
TCIE
TC
0
T8
R6
T6
TNP0
SBR5
RSRC
0
0
0
RIE
RDRF
0
0
R5
T5
SBR12
SBR4
M
0
0
0
ILIE
IDLE
TXPOL
0
R4
T4
1 _{Those registers are accessible if the AMAP bit in the SCI0SR2 register is set to zero}
2 _{Those registers are accessible if the AMAP bit in the SCI0SR2 register is set to one}
Bit 3
SBR11
SBR3
WAKE
0
0
0
TE
OR
RXPOL
0
R3
T3
Bit 2
SBR10
Bit 1
SBR9
SBR2
SBR1
ILT
PE
BERRV
0
BERRIF
BERRIE
BERRM1 BERRM0
RE
RWU
NF
FE
BRK13
0
TXDIR
0
R2
R1
T2
T1
Bit 0
SBR8
SBR0
PT
BKDIF
BKDIE
BKDFE
SBK
PF
RAF
0
R0
T0
MC9S12XHZ512 Data Sheet, Rev. 1.06
952
Freescale Semiconductor