S912XHZ512F1VAG Datasheet, PDF (338/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 7 Clocks and Reset Generator (S12CRGV6)
NOTE
Write to this register initializes the lock detector bit and the track detector
bit.
7.3.2.3 Reserved Register (CTFLG)
This register is reserved for factory testing of the CRG module and is not available in normal modes.
Module Base +0x_02
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-6. Reserved Register (CTFLG)
Read: Always reads 0x_00 in normal modes
Write: Unimplemented in normal modes
NOTE
Writing to this register when in special mode can alter the CRG
fucntionality.
7.3.2.4 CRG Flags Register (CRGFLG)
This register provides CRG status bits and flags.
Module Base +0x_03
R
W
Reset
7
RTIF
0
6
PORF
1
5
LVRF
2
4
LOCKIF
0
3
LOCK
0
2
TRACK
0
1. PORF is set to 1 when a power on reset occurs. Unaffected by system reset.
2. LVRF is set to 1 when a low-voltage reset occurs. Unaffected by system reset.
= Unimplemented or Reserved
Figure 7-7. CRG Flags Register (CRGFLG)
Read: Anytime
Write: Refer to each bit for individual write conditions
1
SCMIF
0
0
SCM
0
MC9S12XHZ512 Data Sheet, Rev. 1.06
338
Freescale Semiconductor