S912XHZ512F1VAG Datasheet, PDF (833/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 24 Interrupt (S12XINTV1)
• Wait mode
In wait mode, the XINT module is frozen. It is however capable of either waking up the CPU if an
interrupt occurs or waking up the XGATE if an XGATE request occurs. Please refer to
Section 24.5.3, “Wake Up from Stop or Wait Mode” for details.
• Stop Mode
In stop mode, the XINT module is frozen. It is however capable of either waking up the CPU if an
interrupt occurs or waking up the XGATE if an XGATE request occurs. Please refer to
Section 24.5.3, “Wake Up from Stop or Wait Mode” for details.
• Freeze mode (BDM active)
In freeze mode (BDM active), the interrupt vector base register is overridden internally. Please
refer to Section 24.3.1.1, “Interrupt Vector Base Register (IVBR)” for details.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
833