S912XHZ512F1VAG Datasheet, PDF (397/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

9.3.2.8
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4) Block Description
Reserved Register 0 (ATDTEST0)
Module Base + 0x0008
7
6
5
4
3
2
1
0
R
u
u
u
u
u
u
u
u
W
Reset
1
0
0
0
0
0
0
0
= Unimplemented or Reserved
u = Unaffected
Figure 9-10. Reserved Register 0 (ATDTEST0)
Read: Anytime, returns unpredictable values
Write: Anytime in special modes, unimplemented in normal modes
NOTE
Writing to this register when in special modes can alter functionality.
9.3.2.9 ATD Test Register 1 (ATDTEST1)
This register contains the SC bit used to enable special channel conversions.
Module Base + 0x0009
7
6
5
4
3
2
1
0
R
u
u
u
u
u
u
u
SC
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
u = Unaffected
Figure 9-11. Reserved Register 1 (ATDTEST1)
Read: Anytime, returns unpredictable values for bit 7 and bit 6
Write: Anytime
NOTE
Writing to this register when in special modes can alter functionality.
Table 9-19. ATDTEST1 Field Descriptions
Field
0
SC
Description
Special Channel Conversion Bit — If this bit is set, then special channel conversion can be selected using
CC, CB, and CA of ATDCTL5. Table 9-20 lists the coding.
0 Special channel conversions disabled
1 Special channel conversions enabled
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
397