S912XHZ512F1VAG Datasheet, PDF (158/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 3 512 Kbyte Flash Module (S12XFTX512K4V3)
START
Read: FCLKDIV register
Clock Register
Written
Check
FDIVLD
Set?
yes
no
Write: FCLKDIV register
NOTE: FCLKDIV needs to
be set once after each reset.
Read: FSTAT register
Address, Data,
Command
Buffer Empty Check
CBEIF
no
Set?
yes
Access Error and
Protection Violation
Check
1.
Simultaneous
Multiple Flash Block
Decision
2.
ACCERR/
yes
PVIOL
Set?
no
Write: FSTAT register
Clear ACCERR/PVIOL 0x30
Write: Flash Address to start
compression and number of word
addresses to compress (max 16,384)
NOTE: address used to select
Flash block; data ignored.
Next
Flash
Block?
yes
Decrement Global Address
by 128K
no
Write: FCMD register
Data Compress Command 0x06
3.
Write: FSTAT register
Clear CBEIF 0x80
Read: FSTAT register
Bit Polling for
Command Completion
Check
CCIF
no
Set?
yes
Read: FDATA registers
Data Compress Signature
Signature
no
Valid?
yes
EXIT
Erase and Reprogram
Flash Sector(s) Compressed
Figure 3-26. Example Data Compress Command Flow
MC9S12XHZ512 Data Sheet, Rev. 1.06
158
Freescale Semiconductor