S912XHZ512F1VAG Datasheet, PDF (710/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
Module Base + 0x003D
7
R TC7
6
TC6
5
TC5
4
TC4
3
TC3
2
TC2
1
TC1
0
TC0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-64. Timer Input Capture Holding Register 2 Low (TC2H)
Module Base + 0x003E
15
R TC15
14
TC14
13
TC13
12
TC12
11
TC11
10
TC10
9
TC9
8
TC8
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-65. Timer Input Capture Holding Register 3 High (TC3H)
Module Base + 0x003F
7
R TC7
6
TC6
5
TC5
4
TC4
3
TC3
2
TC2
1
TC1
0
TC0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-66. Timer Input Capture Holding Register 3 Low (TC3H)
Read: Anytime
Write: Has no effect.
All bits reset to zero.
These registers are used to latch the value of the input capture registers TC0–TC3. The corresponding
IOSx bits in TIOS should be cleared (see Section 19.4.1.1, “IC Channels”).
19.4 Functional Description
This section provides a complete functional description of the ECT block, detailing the operation of the
design from the end user perspective in a number of subsections.
MC9S12XHZ512 Data Sheet, Rev. 1.06
710
Freescale Semiconductor