S912XHZ512F1VAG Datasheet, PDF (668/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 18 Pulse-Width Modulator (S12PWM8B8CV1)
Either left aligned or center aligned output mode can be used in concatenated mode and is controlled by
the low order CAEx bit. The high order CAEx bit has no effect.
Table 18-11 is used to summarize which channels are used to set the various control bits when in 16-bit
mode.
Table 18-11. 16-bit Concatenation Mode Summary
CONxx
CON67
CON45
CON23
CON01
PWMEx
PWME7
PWME5
PWME3
PWME1
PPOLx
PPOL7
PPOL5
PPOL3
PPOL1
PCLKx
PCLK7
PCLK5
PCLK3
PCLK1
CAEx
CAE7
CAE5
CAE3
CAE1
PWMx
Output
PWM7
PWM5
PWM3
PWM1
18.4.2.8 PWM Boundary Cases
Table 18-12 summarizes the boundary conditions for the PWM regardless of the output mode (left aligned
or center aligned) and 8-bit (normal) or 16-bit (concatenation).
Table 18-12. PWM Boundary Cases
PWMDTYx
PWMPERx
$00
(indicates no duty)
>$00
$00
(indicates no duty)
XX
XX
>$00
$00¹
(indicates no period)
$00¹
(indicates no period)
>= PWMPERx
XX
>= PWMPERx
XX
1 _{Counter = $00 and does not count.}
PPOLx
1
0
1
0
1
0
PWMx Output
Always low
Always high
Always high
Always low
Always high
Always low
18.5 Resets
The reset state of each individual bit is listed within the Section 18.3.2, “Register Descriptions” which
details the registers and their bit-fields. All special functions or modes which are initialized during or just
following reset are described within this section.
• The 8-bit up/down counter is configured as an up counter out of reset.
• All the channels are disabled and all the counters do not count.
MC9S12XHZ512 Data Sheet, Rev. 1.06
668
Freescale Semiconductor