S912XHZ512F1VAG Datasheet, PDF (876/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 25 Memory Mapping Control (S12XMMCV3)
Table 25-21 shows the address boundaries of each chip select and the relationship with the implemented
resources (internal) parameters.
Table 25-21. Global Chip Selects Memory Space
Chip Selects
Bottom Address
Top Address
CS3
CS2
CS2³
0x00_0800
0x10_0000
0x14_0000
0x0F_FFFF minus RAMSIZE¹
0x13_FFFF minus EEPROMSIZE²
0x1F_FFFF
CS1
CS0⁴
0x20_0000
0x40_0000
0x3F_FFFF
0x7F_FFFF minus FLASHSIZE⁵
1 _{External RPAGE accesses in (NX, EX and ST)}
2 _{External EPAGE accesses in (NX, EX and ST)}
3 _{When ROMHM is set (see ROMHM in Table 25-19) the CS2 is asserted in the space occupied by this}
on-chip memory block.
4 _{When the internal NVM is enabled (see ROMON in Section 25.3.2.5, “MMC Control Register (MMCCTL1))}
the CS0 is not asserted in the space occupied by this on-chip memory block.
5 _{External PPAGE accesses in (NX, EX and ST)}
MC9S12XHZ512 Data Sheet, Rev. 1.06
876
Freescale Semiconductor