S912XHZ512F1VAG Datasheet, PDF (598/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 15 Serial Communication Interface (S12SCIV5)
15.5.3.1.6 RXEDGIF Description
The RXEDGIF interrupt is set when an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the
RXD pin is detected. Clear RXEDGIF by writing a “1” to the SCIASR1 SCI alternative status register 1.
15.5.3.1.7 BERRIF Description
The BERRIF interrupt is set when a mismatch between the transmitted and the received data in a single
wire application like LIN was detected. Clear BERRIF by writing a “1” to the SCIASR1 SCI alternative
status register 1. This flag is also cleared if the bit error detect feature is disabled.
15.5.3.1.8 BKDIF Description
The BKDIF interrupt is set when a break signal was received. Clear BKDIF by writing a “1” to the
SCIASR1 SCI alternative status register 1. This flag is also cleared if break detect feature is disabled.
15.5.4 Recovery from Wait Mode
The SCI interrupt request can be used to bring the CPU out of wait mode.
15.5.5 Recovery from Stop Mode
An active edge on the receive input can be used to bring the CPU out of stop mode.
MC9S12XHZ512 Data Sheet, Rev. 1.06
598
Freescale Semiconductor