S912XHZ512F1VAG Datasheet, PDF (709/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
19.3.2.32 Timer Input Capture Holding Registers 0–3 (TCxH)
Module Base + 0x0038
15
R TC15
14
TC14
13
TC13
12
TC12
11
TC11
10
TC10
9
TC9
8
TC8
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-59. Timer Input Capture Holding Register 0 High (TC0H)
Module Base + 0x0039
7
R TC7
6
TC6
5
TC5
4
TC4
3
TC3
2
TC2
1
TC1
0
TC0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-60. Timer Input Capture Holding Register 0 Low (TC0H)
Module Base + 0x003A
15
R TC15
14
TC14
13
TC13
12
TC12
11
TC11
10
TC10
9
TC9
8
TC8
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-61. Timer Input Capture Holding Register 1 High (TC1H)
Module Base + 0x003B
7
R TC7
6
TC6
5
TC5
4
TC4
3
TC3
2
TC2
1
TC1
0
TC0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-62. Timer Input Capture Holding Register 1 Low (TC1H)
Module Base + 0x003C
15
R TC15
14
TC14
13
TC13
12
TC12
11
TC11
10
TC10
9
TC9
8
TC8
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-63. Timer Input Capture Holding Register 2 High (TC2H)
MC9S12XHZ512 Data Sheet Rev. 1.06
Freescale Semiconductor
709