S912XHZ512F1VAG Datasheet, PDF (743/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 21 Background Debug Module (S12XBDMV2)
Global Register
Address Name
0x7FFF07 BDMCCRH R
W
Bit 7
0
0x7FFF08 BDMGPR R
BGAE
W
0x7FFF09 Reserved R
0
W
0x7FFF0A Reserved R
0
W
0x7FFF0B Reserved R
0
W
6
0
BGP6
0
0
0
5
0
BGP5
0
0
0
4
0
BGP4
0
0
0
3
2
1
0
CCR10 CCR9
BGP3
BGP2
BGP1
0
0
0
0
0
0
0
0
0
Bit 0
CCR8
BGP0
0
0
0
= Unimplemented, Reserved
= Implemented (do not alter)
X
= Indeterminate
0
= Always read zero
Figure 21-2. BDM Register Summary (continued)
21.3.2.1 BDM Status Register (BDMSTS)
Register Global Address 0x7FFF01
R
W
Reset
Special Single-Chip Mode
Emulation Modes
(if modes available)
All Other Modes
7
ENBDM
0¹
1
0
6
5
BDMACT
0
4
SDV
1
0
0
0
0
0
0
0
0
= Unimplemented, Reserved
3
2
1
0
TRACE
UNSEC
0
CLKSW
0
0
0³
0
0
1²
0
0
0
0
0
0
= Implemented (do not alter)
0
= Always read zero
1 _{ENBDM is read as 1 by a debugging environment in special single chip mode when the device is not secured or secured but}
fully erased (non-volatile memory). This is because the ENBDM bit is set by the standard firmware before a BDM command
can be fully transmitted and executed.
2 _{CLKSW is read as 1 by a debugging environment in emulation modes when the device is not secured and read as 0 when}
secured if emulation modes available.
3 _{UNSEC is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased,}
else it is 0 and can only be read if not secure (see also bit description).
Figure 21-3. BDM Status Register (BDMSTS)
MC9S12XHZ512 Data Sheet Rev. 1.06
Freescale Semiconductor
743