S912XHZ512F1VAG Datasheet, PDF (70/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
Table 2-3. DDRA Field Descriptions
Field
7:0
Data Direction Port A
DDRA[7:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
2.3.1.4 Port B Data Direction Register (DDRB)
Module Base + 0x0055
7
R
DDRB7
W
6
DDRB6
5
DDRB5
4
DDRB4
3
DDRB3
2
DDRB2
1
DDRB1
0
DDRB0
Reset
0
0
0
0
0
0
0
0
Figure 2-5. Port B Data Direction Register (DDRB)
Read: Anytime. Write: Anytime.
This register configures port pins PB[7:0] as either input or output.If a LCD frontplane driver is enabled
(and LCD module is enabled), it outputs an analog signal to the corresponding pin and the associated Data
Direction Register bit has no effect. If a LCD frontplane driver is disabled (or LCD module is disabled),
the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin.
Table 2-4. DDRB Field Descriptions
Field
7:0
Data Direction Port B
DDRB[7:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
MC9S12XHZ512 Data Sheet, Rev. 1.06
70
Freescale Semiconductor