S912XHZ512F1VAG Datasheet, PDF (823/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 23 External Bus Interface (S12XEBIV3)
Table 23-17. Access in Normal Expanded Mode
Access
DATA[15:8]
DATA[7:0]
RE WE UDS LDS
I/O data(addr) I/O data(addr)
Word write of data on DATA[15:0] at an even and even+1 address 1 0 0
Byte write of data on DATA[7:0] at an odd address
10 1
Byte write of data on DATA[15:8] at an even address
10 0
0 Out data(even) Out data(odd)
0 In
x
Out data(odd)
1 Out data(even) In
x
Word read of data on DATA[15:0] at an even and even+1 address 0 1 0
Byte read of data on DATA[7:0] at an odd address
01 1
Byte read of data on DATA[15:8] at an even address
01 0
Indicates No Access
11 1
Unimplemented
11 1
11 0
0 In data(even) In data(odd)
0 In
x
In data(odd)
1 In data(even) In
x
1 In
x
In
x
0 In
x
In
x
1 In
x
In
x
23.4.5.2 Emulation Modes and Special Test Mode
In emulation modes and special test mode, the external signals LSTRB, RW, and ADDR0 indicate the
access type (read/write), data size and alignment of an external bus access. Misaligned accesses to the
internal RAM and misaligned XGATE PRR accesses in emulation modes are the only type of access that
are able to produce LSTRB = ADDR0 = 1. This is summarized in Table 23-18.
Table 23-18. Access in Emulation Modes and Special Test Mode
Access
Word write of data on DATA[15:0] at an even and even+1
address
Byte write of data on DATA[7:0] at an odd address
Byte write of data on DATA[15:8] at an even address
Word write at an odd and odd+1 internal RAM address
(misaligned — only in emulation modes)
Word read of data on DATA[15:0] at an even and even+1
address
Byte read of data on DATA[7:0] at an odd address
Byte read of data on DATA[15:8] at an even address
Word read at an odd and odd+1 internal RAM address
(misaligned - only in emulation modes)
DATA[15:8]
DATA[7:0]
RW LSTRB ADDR0
I/O data(addr) I/O data(addr)
0
0
0 Out data(even) Out data(odd)
0
0
0
1
0
1
1
In
x
Out data(odd)
0 Out data(odd) In
x
1 Out data(odd+1) Out data(odd)
1
0
0
In data(even) In data(even+1)
1
0
1
1
1
1
1
In
x
In data(odd)
0
In data(even) In
x
1
In data(odd+1) In data(odd)
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
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