S912XHZ512F1VAG Datasheet, PDF (73/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.3 Port E
Port E pins can be used for either general-purpose I/O, or the liquid crystal display (LCD) driver, or the
external bus control outputs R/W, WE, LSTRB, LDS and RE, the free running clock outputs ECLK and
ECLKX2, or the inputs TAGHI, TAGLO, MODA, MODB, EROMCTL, XCLKS and interrupts IRQ and
XIRQ. Refer to the LCD block description chapter for information on enabling and disabling the LCD and
its frontplane drivers. Refer to the S12X_EBI block description chapter for information on external bus.
Port E pin PE[7] can be used for either general-purpose I/O, or as the free-running clock ECLKX2 output
running at the core clock rate, or the frontplane driver FP22. The clock ECLKX2 output is always enabled
in emulation modes.
Port E pin PE[4] can be used for either general-purpose I/O or as the free-running clock ECLK output
running at the bus clock rate or at the programmed divided clock rate. The clock output is always enabled
in emulation modes.
Port E pin PE[1] can be used for either general-purpose input or as the level- or falling edge-sensitive IRQ
interrupt inpu. IRQ will be enabled by setting the IRQEN configuration bit and clearing the I-bit in the
CPU’s condition code register. It is inhibited at reset so this pin is initially configured as a simple input
with a pull-up.
Port E pin PE[0] can be used for either general-purpose input or as the level-sensitive XIRQ interrupt
input. XIRQ can be enabled by clearing the X-bit in the CPU’s condition code register. It is inhibited at
reset so this pin is initially configured as a high-impedance input with a pull-up.
2.3.3.1 Port E I/O Register (PTE)
Module Base + 0x0051
R
W
XEBI:
7
PTE7
XCLKS¹
or
ECLKX2
6
PTE6
MODB¹
or
TAGHI
5
PTE5
MODA¹
or
TAGLO
or
RE
4
PTE4
ECLK
3
PTE3
EROMCTL¹
or
LSTRB
or
LDS
2
PTE2
R/W
or
WE
1
PTE1
IRQ
0
PTE0
XIRQ
LCD: FP22
FP21
FP20
Reset
0
0
0
0
0
0
—²
—²
Figure 2-10. Port E I/O Register (PTE)
1 _{Function active when RESET asserted.}
2 _{These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated}
pin values.
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDREx) is set to 1 (output), a read returns the value of the I/O register
bit.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
73